Introduction: Increasing The Resolution of Analog-to-Digital Conversion by Oversampling
Every analog-to-digital conversion is designed for specific resolution depending on the bit (binary digit) width of the conversion. For example, a 10 bit ADC with 5V reference would have 5V/1024 resolution or about 4.883 mV. The intrinsic error related to the resolution is the digital-quantization error of ±0.5 bit (or 2.441 mV in the case of the example). Oversampling is done by reading the input several times, but the input is added with a noise that moves the input up and down across 1 bit level. The reading is done many times and then averaged to get more consistent reading at the expected new resolution (bit-width). Without noise addition, a very stable signal on the input would produce a consistent reading no matter how many times the reading is repeated, so averaging many samples won’t increase the resolution.
Some Difficulties with Noise Addition
The ideal source of the noise would be a Gaussian white noise, but the generation of this noise is complicated. If the noise is truly random, the noise component for each samples gathered during the oversampling would be spread evenly within 1 bit width of the original ADC resolution. This ideal condition enable the system to improve the resolution by 1/2 bit if the sampling frequency is doubled. In real application, the oversampling frequency should be much higher than this ideal condition since the random nature of the noise wouldn’t be distributed evenly for small number of samples. As presented in the reference , oversampling would work when some complex conditions are satisfied:
The noise must approximate white noise with uniform power spectral density over the frequency band of interest.
The noise amplitude must be sufficient to cause the input signal to change randomly from sample to sample by amounts comparable to at least the distance between two adjacent codes (i.e.,1 LSB..)
The input signal can be represented as a random variable that has equal probability of existing at any value between two adjacent ADC codes.
A simple quasi-triangular noise shown in Figure 1 is proposed in reference  to avoid complication in white noise generation. The circuit is simple, but other complexities are introduced:
- The peak-to-peak amplitude of this quasi-triangle signal should be exactly 1 bit width or its multiplication. This lead to calibration problem which is difficult for such small noise amplitude. Please comment on this my opinion if I’m wrong.
- The quasi-triangle signal frequency should be uncorrelated with the sampling frequency if the oversampling period is longer than this additive signal period.
- Faster oversampling can be implemented to acquire all the over-sampled samples within one period of the quasi-triangle signal, but the noise signal should be very stable to give consistent boundary or a synchronization method should be implemented for reading the samples.
For microcontroller that has multiplexer for implementing multichannel inputs (such as STM32F1 series), we can expand the signal into several points that ranges from (signal -0.5 bit) to (signal + 0.5 bit). I have designed such circuit, and the schematic diagram is shown in the Figure 2.
The employed operational amplifiers should have offset adjustment, so we can set the first op-amp to give -0.5 bit offset and the second to give +0.5 bit offset. The ADC of STM32F1 series has 12 bit resolution with a fixed analog reference (3.3V), so the bit width is 3.3V/(2^12) = 0.8 mV. With 8 channel expansion, the expected result would be 15 bit resolution or 0.1 mV resolution. To be precise, the range should be expanded by the bit-width of the original ADC resolution minus the bit-width of the expected final resolution, or 0.8mV – 0.1mV = 0.7 mV. Using a high precision voltmeter, we can set the first op-amp to add -350 uV offset and the second to add +350 uV offset. The voltage dividers R1 – R7 should be chosen as low as possible to minimize the loading effect of the multiplexer input, but the cross-current between the first op-amp and the second op-amp outputs should be kept small to be easily handled. With only 700 uV difference, resistor values around 10-15 ohm results in total series resistance of 70 – 105 Ohm and produce the cross current of 6.67-10 uA, and that should be easily handled by the op-amp. To get the 15-bit reading, just sum up the reading of all channels, no need any shifting or division.
Offset Calibration Method
For lowering the cost and simplify the calibration process, R9 trimmer potentiometer can be omitted. The offset calibration then can be done by adjusting R8 only. Just make sure that U2 and U3 are of the same type to ensure that they have identical characteristics. It is recommended that the input level is held at half of the reference voltage, then measure the voltage across U2 and U3 outputs and adjust R8 until gets 700uV reading. The modification that omit the second offset adjustment has been successfully tested, and the final circuit is shown in the schematic diagram below:
The -Vcc supply should be biased to negative in to enable the op-amp produce a correct result around zero volt input, and it has been successfully tested using a positive supply to negative supply converter using 555 IC to drive a charge pump circuitry, which produce around -2.5V supply from 5V positive supply.
- Improving ADC Resolution by Oversampling and Averaging, Silicon Labs Application Note,
Rev. 1.3 7/13, 2013
- How to get the best ADC accuracy in STM32 microcontrollers, ST Microelectronics Application Note, 2017